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TB1311AFG 2006-05-29 1 toshiba bi-cmos integrated circuit silicon monolithic TB1311AFG audio sw, video sw, sync separation and h/v frequency counter ic for tvs the TB1311AFG includes audio and video sw blocks, prefilters for a/d converters, sync separators, and an h/v format detector for tv signals. the TB1311AFG contributes to a reduction in the proportion of the pcb occupied by lcr filters and to the simplification of designs on analog interfaces. the TB1311AFG has an i 2 cbus interface through which various functions can be controlled. features audio sw block ? audio (l/r) inputs ? audio (l/r) output: 3 channels audio block ? attenuator video sw block ? cvbs inputs ? y/c inputs ? component video inputs (co-use as rgb inputs) ? scart inputs ? output: 2 channels ? monitor output video block ? gain switching: -3 db / 0 db / +3 db ? bandwidth filter: prefilter for adc; 4.5 to 46 mhz variable sync separation block ? supports 525/30p/60i/60p, 625/50i/50p, 750/50p/60p, 1125/24p/24sf/25p/30p/50i/60i/50p/60p, 1250/50i, vga @60, svga@60, xga@60, sxga@60, uxga@60 ? hd/vd input: 1 channel; positive and negative input acceptable ? hd/vd output: positive and negative output selectable ? masking pseudo-sync for the copyguard signal others ? line detector for japanese d-pin ? s2, s1, insertion detection for s-pin ? horizontal and vertical frequency counter ? format detection circuit to input signal ? no-input detection ? automatic sync process switching mode ? programmable number of audio/video inputs p-qfp80-1420-0.80c weight: 1.6 g (typ.)
TB1311AFG 2006-05-29 2 block diagram 1 (simplified overview) this ic does not support weak signals, ghost signals or other nonstandard signals. some functional blocks, circuits, or constants may be omitted or simplified in the block diagram for explanatory purposes.
TB1311AFG 2006-05-29 3 block diagram 2 (video block) some functional blocks, circuits, or constants may be omitted or simplified in the block diagram for explanatory purposes.
TB1311AFG 2006-05-29 4 block diagram 3 (audio block) ar1 in 35 al1 in 37 ar2 in 42 al2 in 43 ar3 in 52 al3 in 54 ar4 in 56 al4 in 58 ar5 in 62 al5 in 63 ar6 in 72 al6 in 74 ar7 in 76 al7 in 78 ar8 in/dc1(s3) 39 40 al8 in/dc2(s4) ar9 in/dc4(line3-1) 46 48 al9 in/dc5(line2-1) ar10 in/dc9(line3-2) 66 68 al10 in/dc10(line2-2) att att att att att att att att att att att att att att att att att att att att al1 out 5 ar1 out 7 al2 out 18 ar2 out 20 al3 out 1 ar3 out 3 other block au1 out au2 out au3 out au2 fix au1 fix total 0db total 0db total 0db total 0db au2 att au1 att other block other block other block other block other block some functional blocks, circuits, or constants may be omitted or simplified in the block diagram for explanatory purposes.
TB1311AFG 2006-05-29 5 block diagram 4 (other blocks) i2cbus freq counter this ic does not support weak signals, ghost signals or other nonstandard signals. some functional blocks, circuits, or constants may be omitted or simplified in the block diagram for explanatory purposes.
TB1311AFG 2006-05-29 6 pin assignment v/s gnd sy1 in ar3 in y3/g3 in fb1 in/dc3(sw line1) ar2 in y1/g1 in cb1/b1 in al4 in dc7(s1) al5 in cvbs6 in cr1/r1 in hd out vd out sync filter cb1/b1 out au vcc (9v) monitor out cvbs1 out y1/g1 out ar1 out cr2/r2 out cr1/r1 out al2 out al3 out y2/g2 out cb2/b2 out ar5 in sc1 in ar4 in al3 in ar9 in/dc4(line3-1) al2 in fb2 out ar2 out cvbs2 out sync2 in v/s vcc (5v) fb1 out al1 out ar3 out cvbs5 in al9 in/dc5(line2-1) fb3 in/dc6(line1-1) cr3/r3 in cb3/b3 in fb2 in/ dc8(sw line2)
TB1311AFG 2006-05-29 7 pin functions the equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. pin no. pin name function interface circuit input signal/output signal 29 v dd (3.3 v) v cc pin for the logical circuits. supply power through a resistor from pin 11 as in the application circuit. this pin voltage is clipped to 3.3 v (typ.) by the internal regulator. 29 11 27 500 3.3v 3.3 v (typ.) 27 vss gnd pin for the logical circuits. ? ? 11 v/s v cc (5 v) v cc pin for the sync and video circuits. connect 5.0 v (typ.) ? 5.0 v (typ.) 16 v/s gnd gnd pin for the sync and video circuits. ? ? 24 au v cc (9 v) v cc pin for the audio circuits. connect 9.0 v (typ.) ? 9.0 v (typ.) 32 au gnd gnd pin for the audio circuits. ? ? 36 38 41 61 57 77 cvbs3 in cvbs4 in cvbs5 in cvbs6 in sy1 in sy2 in cvbs or y input pin. input the cvbs or y signal in ntsc, pal or secam via a clamp capacitor. sync tip level: 2.3 v (typ.) y/cvbs signal amplitude: 1.0 vp-p (with sync) 59 79 sc1 in sc2 in chroma signal input pin. input c signal via a capacitor. the voltage of this pin is detected and the status is returned to the i 2 cbus read functions, s4 or s8. it is used for detecting whether the s-pin is connected or not. 1v 100.2k 3v 2.9 v bias (typ.) burst signal amplitude: 0.3 vp-p 49 69 55 75 y1/g1 in y2/g2 in y3/g3 in y4/g4 in y, g or cvbs input pin. input the signal via a clamp capacitor. the clamp system is selectable by clamp1, 2, 3 or 4 registers. 11 16 49 55 69 75 3v/1.5v 200 100.2k 200 3v sync tip level: 2.3 v (typ.) bias level: 2.9 v (typ.) y/g/cvbs signal amplitude: 1.0 vp-p (with sync) 47 67 53 73 cb1/b1 in cb2/b2 in cb3/b3 in cb4/b4 in cb, b or c input pin. input the signal via a capacitor. 1v 100.2k 3v 2.9 v bias (typ.) cb/b signal amplitude: 0.7 vp-p (without sync) burst signal amplitude: 0.3 vp-p
TB1311AFG 2006-05-29 8 pin no. pin name function interface circuit input signal/output signal 45 65 cr1/r1 in cr2/r2 in cr, r or c input pin. input the signal via a capacitor. 1v 100.2k 3v 2.9 v bias (typ.) cr/r signal amplitude: 0.7 vp-p (without sync) burst signal amplitude: 0.3 vp-p 51 71 cr3/r3 in cr4/r4 in cr, r or cvbs input pin. input the signal via a capacitor. the clamp system is changed according to cbcr pin3 or 4 registers. 11 16 51 71 3v/1.5v 200 100.2k 200 3v sync tip level: 2.3 v (typ.) bias level: 2.9 v (typ.) cr/r signal amplitude: 0.7 vp-p (without sync) cvbs signal amplitude: 1.0 vp-p (with sync) 35 37 42 43 52 54 56 58 62 63 72 74 76 78 ar1 in al1 in ar2 in al2 in ar3 in al3 in ar4 in al4 in ar5 in al5 in ar6 in al6 in ar7 in al7 in audio input pin. input the signal via a resistor and a capacitor. when the resistor value is 5.6 k ? , the internal gain becomes 0 db (typ.). 24 40.2k 32 58 62 63 72 74 76 78 1pf 4.5v 35 37 42 43 52 54 56 47k bias level: 4.4 v (typ.) audio input: 2.8 p-p (100%) 39 40 46 48 66 68 ar8 in/dc1 al8 in/dc2 ar9 in/dc4 al9 in/dc5 ar10 in/dc9 al10 in/dc10 audio or dc voltage input pin. the input type is changed by au8 pin, au9 pin or au10 pin. in the case of use as audio input, input the signal via a resistor and a capacitor. when the resistor value is 5.6 k ? , the internal gain becomes 0 db (typ.). in the case of use as dc voltage input, input the signal via a resistor for protection. 24 40k 32 39 40 46 48 66 68 11 16 th1 th2 200 76k bias level: 4.4 v (typ.) audio input: 2.8 p-p (100%) 44 64 50 70 fb1 in/dc3 fb2 in/dc8 fb3 in/dc6 fb4 in/dc11 fb (fast blanking) signal or dc voltage input pin. connect a resistor between this pin and gnd. in the case of use as dc voltage input, input the signal via a resistor for protection. 3.25k 1v 3v fb input: 60 80 dc7 dc12 dc voltage input. input the signal via a resistor for protection purposes. this pin is also used as a test signal output pin for shipping only. 1v 3v 1k dc
TB1311AFG 2006-05-29 9 pin no. pin name function interface circuit input signal/output signal 33 15 sync1 in sync2 in composite sync input pin to separate into h- and v-sync. input the signal via a clamp capacitor. remark: sync1 in is not available, when a-sync = 1 (on). sync tip level: 1.8 v (typ.) or 1vp-p 31 30 hd in vd in hd or vd input pin. input a separated horizontal or vertical sync signal (1.0 to 2.0 vp-p) via a resistor and a coupling capacitor. the polarity of the input signal is detected and its leading edge becomes a timing trigger. 1.45 v bias (typ.) or 4 6 8 10 17 19 21 23 cvbs1 out y1/g1 out cb1/b1 out cr1/r1 out cvbs2 out y2/g2 out cb2/b2 out cr2/r2 out video signal output pin. refer to bus control functions for details of the output from each pin. 11 16 4 6 8 10 17 19 21 23 100 ac: -3, 0 or +3 db (typ.) 5 7 18 20 1 3 al1 out ar1 out al2 out ar2 out al3 out ar3 out audio signal output pin. refer to bus control functions for details of the output from each pin. 24 32 1 3 5 7 18 20 2 monitor out video signal output pin for a monitor output. refer to bus control functions for details of the output from the pin. ac: +6 db (typ.) 34 yvi out video signal output pin for the sync separation circuit. refer to bus control functions for details of the output from the pin. 11 16 2 34 ac: 0 db (typ.) 12 13 hd out vd out hd or vd output pin. the polarity of the output is selectable by hv-pol register. the tailing edge of the vd-out has a jitter. use the leading edge only. or 9 22 fb1 out fb2 out fb output pin. note: if necessary, a resistor can be added between the pin and gnd to improve the transient of the falling edge. the value of the resistor must be 440 ? or more. however, when the resistor is added, the leak pulse from fb edges to video signals is also increased. 11 16 9 12 13 22 100 14 sync filter a filter pin for sync detection. connect a capacitor between this pin and gnd. ?
TB1311AFG 2006-05-29 10 pin no. pin name function interface circuit input signal/output signal 28 xtal crystal connection pin. connect a 3.579545 mhz crystal for ntsc demodulation to generate internal clocks. ? 25 sda sda pin for i 2 cbus. 25 27 11 50 5k ack h to l: 1.3 v (typ.) l to h: 2.1 v (typ.) 26 scl scl pin for i 2 cbus. 26 27 11 5k h to l: 1.3 v (typ.) l to h: 2.1 v (typ.)
TB1311AFG 2006-05-29 11 bus control map write mode slave address: de h sa d7 d6 d5 d4 d3 d2 d1 d0 preset 00 cvbs1out fc half1 ycbcr1out 00000000 01 cvbs2out fc half2 ycbcr2out 00000000 02 (0) filpass2 filpass1 yc mix mon out 00000000 03 f0 sw1 bandwidth1 00000000 04 f0 sw2 bandwidth2 00000000 05 cvbs2 gain ycbcr2 gain cvbs1 gain ycbcr1 gain 00000000 06 cbcr pin4 cbcr pin3 cbcr pin2 cbcr pin1 clamp4 clamp3 clamp2 clamp1 00000000 07 fb2 dl fb2 mute fb2 out fb1 dl fb1 mute fb1 out 00000000 08 au2 out au1 out 00010001 09 au1 fix au1 att 00000000 0a au2 fix au2 att 00000000 0b au10 pin au9 pin au8 pin (0) au3 out 00000001 0c hv-sep2 hv-sep1 (0) (0) sync lpf2 sync lpf1 00000000 0d a-sync sig lpf (0) (0) yvi out 00000000 0e (0) ps mask v-det hd width hv pol (0) hv det hv out 00000000 0f h dmy v dmy fb2 pin-m hv freq2 00000000 10 h count max (0) h count min 00000000 11 sig det n sig reset n 00000000 12 (0)test1 fb2 pin-l sig reset sig sw sig det impe sig det lvl 00000000 13 (00000000) test2 00000000 14 (00000000) test3 00000000 remark: sa = sub-address. note: set 0 (zero) on bits written as (0). read mode slave address: df h d7 d6 d5 d4 d3 d2 d1 d0 0 por h fm2 v fm2 h in v in v-sync-w hd-pol vd-pol 1 h format v format ? 2 fb det2 fb det1 sig det hv-out format 3 dc4 dc3 dc2 dc1 4 dc8 dc7 dc6 dc5 5 dc12 dc11 dc10 dc9 6 s8 s7 s6 s5 s4 s3 s2 s1 7 h freq det 8 v freq det ? : undefined
TB1311AFG 2006-05-29 12 bus control functions write mode register name function preset value cvbs1(2)out selects the output from cvbs1(2) out (pin 4 (17)) for scart connector. 000: mute 001: outputs the same y, selected by ycbcr1(2) out 010: cvbs3 (pin 36) 011: cvbs4 (pin 38) 100: cvbs5 (pin 41) 101: cvbs6 (pin 61) 110: cr3 (as cvbs) (pin 51) 111: cr4 (as cvbs) (pin 71) mute (000) fc half1(2) switches the frequency of bandwidth limit filters for cb/cr the cutoff frequency of bandwidth limit filters for cb/cr is 1/2 to y. 0: off (same for 3 outputs) 1: on (1/2 fc for cb/cr) off (0) ycbcr1(2)out selects the output from y/cb/cr out1(2) (pins 6, 8, 10 (19, 21, 23)). (y out, cb out, cr out) = 0000: mute (mute, mute, mute) 0001: sy1 (pin 57), sc1 (pin 59), mute 0010: sy2 (pin 77), sc2 (pin 79), mute 0011: cvbs3 (pin 36), mute, mute 0100: cvbs4 (pin 38), mute, mute 0101: cvbs5 (pin 41), mute (cr1; pin 45, when cbcr pin1 = 1), mute 0110: cvbs6 (pin 61), mute (cr2; pin 65, when cbcr pin2 = 1), mute 0111: y1 (pin 49), cb1 (pin 47), cr1; pin 45 (mute, when cbcr pin1 = 1) 1000: y2 (pin 69), cb2 (pin 67), cr2; pin 65 (mute, when cbcr pin2 = 1) 1001: y3 (pin 55), cb3 (pin 53), cr3; pin 51 (mute, when cbcr pin3 = 1) 1010: y4 (pin 75), cb4 (pin 73), cr4; pin 71 (mute, when cbcr pin4 = 1) 1011: cr3 (as cvbs) (pin 51), mute, mute 1100: cr4 (as cvbs) (pin 71), mute, mute 1101 to 1111: not available refer also to function descriptions. mute (0000) filpass1(2) switches the bandwidth limit filter 1 (2). 0: off (filters active) 1: on (bypass) off (0) yc mix mixes y with c for monitor out (pin 2). 0: off (for cvbs) 1: mix (y+c) off (0) mon out selects the output from monitor out (pin 2). when yc mix = 1, a mixed signal is output. 0000: mute 0001: sy1 (pin 57) (+sc1 (pin 59)) 0010: sy2 (pin 77) (+sc2 (pin 79)) 0011: cvbs3 (pin 36) 0100: cvbs4 (pin 38) 0101: cvbs5 (pin 41) (+cr1 (pin 45), when cbcr pin1 = 1) 0110: cvbs6 (pin 61) (+cr2 (pin 65), when cbcr pin2 = 1) 0111: y1 (pin 49) (+cb1 (pin 47)) 1000: y2 (pin 69) (+cb2 (pin 67)) 1001: y3 (pin 55) (+cb3 (pin 53)) 1010: y4 (pin 75) (+cb4 (pin 73)) 1011: cr3 (cvbs) (pin 51)) 1100: cr4 (cvbs) (pin 71)) 1101 to 1111: not available refer also to function descriptions. mute (0000) f0 sw1(2) switches the f0 of the bandwidth limit filter for ycbcr(rgb) 0: low 1: high note: this function is not valid for the filter for cvbs. for the cvbs filter, this data is fixed to 0: low. low (0) bandwidth1(2) switches the f0 of the bandwidth limit filter for ycbcr(rgb) and cvbs 0000000: min (low) 1111111: max (high) note: while hd, vd or fb-out is output, according as the f0 is set to lower, the crosstalk from hd, vd, fb or sync-in to video-outs becomes bigger. min 0000000
TB1311AFG 2006-05-29 13 register name function preset value cvbs1(2) gain switches output gain. gain of cvbs1(2)-out output (pin 4 (17)) is controlled. 00: 0 db 01: -3 db 10: + 3 db 11: not available 0 db (00) ycbcr1(2) gain switches output gain. gain of ycbcr1(2)-out outputs (pins 6,8,10 (19, 21, 23)) are controlled. 00: 0 db 01: -3 db 10: + 3 db 11: not available remark: gain = 01 (-3 db) is recommended for the 1125/50p/60p format since this offers superior frequency characteristics to those of other modes. 0 db (00) cbcr pin1 changes cbcr1-in pins function. 0: component cb/cr input (pin 49: y/g, pin 47: cb/b, pin 45: cr/r, pin 41: cvbs) 1: separated c input (pin 49: y, pin 47: c, pin 41: y, pin 45: c) cb/cr input (0) cbcr pin2 changes cbcr2-in pins function. 0: component cb/cr input (pin 69: y/g, pin 67: cb/b, pin 65: cr/r, pin 61: cvbs) 1: separated c input (pin 69: y, pin 67: c, pin 61: y, pin 65: c) cb/cr input (0) cbcr pin3 changes cbcr3-in pins function. 0: component cb/cr input (pin 55: y/g, pin 53: cb/b, pin 51: cr/r) 1: separated c input (pin 55: y, pin 53: c, pin 51: cvbs) cb/cr input (0) cbcr pin4 changes cbcr4-in pins function. 0: component cb/cr input (pin 75: y/g, pin 73: cb/b, pin 71: cr/r) 1: separated c input (pin 75: y, pin 73: c, pin 71: cvbs) cb/cr input (0) clamp1(2,3,4) switches y1 (2, 3, 4) clamping mode. the clamping mode for pin 49 (69, 55, 75) is set. 0: sync tip clamp (for y/g with sync) 1: bias (for rgb without sync) sync tip (0) fb1(2) dl turns on the delay to fb1 (2)-out (pin 9 (22)). 0: off 1: on (+30 ns) off (0) fb1(2) mute mutes fb1 (2)-out (pin 9 (22)). 0: off 1: mute off (0) fb1(2) out switches the output from fb1(2)-out (pin 9 (22)). 00: fb1 (pin 44) 01: fb2 (pin 64) 10: fb3 (pin 50) 11: fb4 (pin 70) fb1 (00) au1(2,3) out switches audio outputs from al/ar1 (2,3)-out (pins 5/7 (18/20, 1/3)). 0000: mute 0001: al/ar1 (pins 37/35) 0010: al/ar2 (pins 43/42) 0011: al/ar3 (pins 54/52) 0100: al/ar4 (pins 58/56) 0101: al/ar5 (pins 63/62) 0110: al/ar6 (pins 74/72) 0111: al/ar7 (pins 78/76) 1000: al/ar8 (pins 40/39) 1001: al/ar9 (pins 48/46) 1010: al/ar10 (pins 68/66) 1011 to 1111: not available al/ar1 (0001)
TB1311AFG 2006-05-29 14 register name function preset value au1(2) fix sets audio volume to al/ar1 (2)-out (pin 5/7 (18/20)) fixed. 0: fixed gain (0 db) 1: off (attenuated by au1(2) att) note: the dc offset on audio outputs occurs when this function is turned on or off. while audio outputs are valid, switching of this function is not available. remark: the gain is defined where the series-connected resistor is 5.6 k ? . fixed (0) au1(2) att attenuates audio volume to al/ar1(2)-out (pins 5/7 (18/20)). 0000000: min 1111111: max min 0000000 au8 pin changes the al/ar8-in pin function. 0: dc input for s-pin (pin 39: dc1(s3), pin 40: dc2(s4)) 1: audio-in8 (pin 39: ar8, pin 40: al8) dc (0) au9 pin changes the al/ar9-in pin function. 0: dc input for d-pin (pin 46: dc4(line2), pin 48: dc5(line1)) 1: audio-in9 (pin 46: ar9, pin 48: al9) dc (0) au10 pin changes the al/ar10-in pin function. 0: dc input for d-pin (pin 66: dc9(line2), pin 68: dc10(line1)) 1: audio-in10 (pin 66: ar10, pin 68: al10) dc (0) hv-sep1(2) switches the separation level. the h/v sync separation level to sync1(2)-in (pin 33 (15)) is switched. 00: low 11: high remark: the separation level is changed according to a ratio of negative sync width per 1h period. low (00) sync lpf1(2) turns on the lpf for the sync-tip clamp. sync lpf1(2) for sync1(2)-in pin changes the speed of the sync-tip clamp response. turn this function on for no-input detection. 0: off 1: on off (0) a-sync automatic sync processing mode. sync processing mode is changed in accordance with the results obtained by the internal format detection circuits. format detection is performed for sync2-in or hd/vd-in signal selected by hv det. the result of detection is returned to h format, v format, h fm2 and v fm2. hv freq setting is invalid when this mode is active. 0: off (manual switching mode by hv freq2 setting) 1: on remark: sync1-in (pin 33) is not available when a-sync = 1 (on). format detection and h/v separation are then executed for sync2-in (pin 15). off (0) sig lpf turns on the lpf for the sync input pin (pin 33; sync1-in). when no-input detection for weak strength signals is required, turn this function on to reduce noise on the input. turn this function off for detections such as h format, v format, h freq det and v freq det. 0: off 1: on off (0) yvi out switches the output from yvi-out (pin 34). 0000: mute 0001: sy1 (pin 57) 0010: sy2 (pin 77) 0011: cvbs3 (pin 36) 0100: cvbs4 (pin 38) 0101: cvbs5 (pin 41) 0110: cvbs6 (pin 61) 0111: y1 (pin 49) 1000: y2 (pin 69) 1001: y3 (pin 55) 1010: y4 (pin 75) 1011: cr3 (as cvbs) (pin 51) 1100: cr4 (as cvbs) (pin 71) 1101 to 1111: not available mute (0000) ps mask switches the mask mode for pseudo-sync. 0: on (normal) 1: off (for ?sync on g?) (1) off mode is used for ?sync on g? input. on (0)
TB1311AFG 2006-05-29 15 register name function preset value v-det switches the v format detection mode. 0: 50/60hz only 1: full detection 50/60 only (0) hd width switches the width of hd-out (pin 12) from sync2-in (pin 15). 0: wide 1: narrow remark: hd width = 1 (narrow) is recommended for the 1125/50p/60p format owing to crosstalk from hd-out to video signals so that spike noises on video signals will occur. wide (0) hv-pol switches the polarity of hd/vd output. the polarity of hd/vd out (pin 12, 13) is set. 0: positive 1: negative positive (0) hv det selects the input for format detection. when a-sync = 0 (manual mode) 0: sync1-in (pin 33) 1: hd/vd-in (pins 31/30) when a-sync = 1 (automatic mode) this function is invalid. the input is selected by hv out. sync (0) hv out switches the outputs from hd/vd-out (pin 12/13). 0: sync2-in (pin 15) 1: hd/vd-in (pins 31/30) sync2-in (0) h dmy outputs the dummy hd at no input. the frequency of the dummy hd output depends on the hv freq2 setting (when a-sync = off) or hv-out format (when a-sync = on). no-input detection is based on h in result. 0: off 1: on (dummy hd output at no input) note: the hd output does not synchronize with input sync, when a-sync = off and when a sync is input. off (0) v dmy outputs the dummy vd at no input. the frequency of the dummy vd output depends on hv freq2 setting (when a-sync = off) or hv-out format (when a-sync = on). no-input detection is based on the v in result. 0: off 1: on (dummy vd output at no input) note: the vd output does not synchronize with input sync, when a-sync = off and when a sync is input. off (0) changes fb2-out pin (pin 22) function. in fb2 pin-m/l = on, the level of pin 22 becomes high when the read registers below change. the level of pin 22 becomes low after the i 2 cbus reading. the pin voltage is used for a sign to detect input signal changes for a microprocessor. for fb2 pin-m/l = on, set a-sync = 1 (on) and fb2 mute = 1 (mute). fb2 pin-m fb2 pin-l mode 0 0 off (fb2-out) 0 1 mode 1 for no-input detection 1 0 mode 2 for format detection 1 1 not available fb2 pin-m, l referential read registers for fb2 pin-m/l = mode 1: fb-det1, sig-det referential read registers for fb2 pin-m/l = mode 2: h-fm2, v-fm2, h-in, v-in, hv-out format off (00)
TB1311AFG 2006-05-29 16 register name function preset value hv freq2 input format setting. set the horizontal and vertical mode according to the format that is input. when a-sync = on mode, this setting is invalid. 00000: 15.625 khz, 50 hz (625i) 00001: 15.75 khz, 60 hz (525i) 00010: 31.25 khz, 50 hz (625p) 00011: 31.5 khz, 60 hz (525p, vga @60 hz) 00100: 28.125 khz, 50 hz (1125/50i) 00101: 33.75 khz, 60 hz (1125/60i) 00110: 37.5 khz, 50 hz (750/50p) 00111: 45 khz, 60 hz (750/60p, xga @60 hz) 01000: 31.25 khz, 50 hz (1250i) 01001: 37.9 khz, 60 hz (svga @60 hz) 01010: 64 khz, 60 hz (1125/60p, sxga @60 hz) 01011: 75 khz, 60 hz (uxga @60 hz) 01100: 56.25 khz, 50 hz (1125/50p) 01101 to 01111: not available 10000: 15.734 khz, 30 hz (525/30p) 10001: 27 khz, 24 hz (1125/24p) 10010: 28.125 khz, 25 hz (1125/25p) 10011: 33.75 khz, 30 hz (1125/30p) 10100: 27 khz, 48 hz (1125/24sf) 10101 to 11111: not available 15.625 khz, 50 hz (00000) h count max selects the h-sync count number for the higher threshold for the no-input detection. 0000: 32 counts 1111: 62 counts (2 counts / step) 32 counts (0000) h count min selects the h-sync count number for the lower threshold for the no-input detection. 000: 16 counts 111: 30 counts (2 counts / step) 16 counts (000) sig det n selects the number of signal detections for the input existence threshold of the no-input detection. 0000: 1 count 0001: 2 counts to 1111: 30 counts (2 counts / step) 1 count (0000) sig reset n selects the number of signal detection for input non-existence threshold of the no-input detection. 0000: 1 count 0001: 2 counts to 1111: 30 counts (2 counts / step) 1 count (0000) sig reset resets the counter for no-input detection. when 1 is sent, the counter for no-input detection is cleared at that time. 0: normal 1: reset normal (0) sig sw selects the input to the counter for no-input detection. 0: sync2-in (pin 15) 1: sync1-in (pin 33) sync2-in (0) sig det impe changes the internal impedance for no-input detection. the time constant of lpf for no-input detection is changed by this function and the capacitor value of sync filter (pin 14). 00: 20 k ? 01: 15 k ? 10: 10 k ? 11: 6 k ? 20 k ? (00) sig det lvl changes the threshold for no-input detection. 00: 0.55 v 01: 0.80 v 10: 1.05 v 11: 1.30 v 0.55 v (00) test1,2,3 test modes for shipping test. set all zero. all 0
TB1311AFG 2006-05-29 17 read mode register name function por power on reset 0: normal 1: register preset after power on, 1 is returned at first read. 0 is returned at second and subsequent reads. h fm2 horizontal format detection 2 0: known 1: unknown detects whether an input is in one of the defined formats or not. this is based on h format data. v fm2 vertical format detection 2 0: known 1: unknown detects whether an input is in one of the defined formats or not. this is based on v format data. h in input detection to horizontal syncs 0: no input 1: signal detected v in input detection to vertical syncs 0: no input 1: signal detected v-sync-w v-sync width detection 0: wide 1: narrow detects v-sync width for detecting 1250i format. under a-sync = 1 (on), v-sync-w shows 1 when vd width from vd-in pin is narrower than approx 69 s, or when v-sync width from sync-in pin is narrower than approx 54 s. hd-pol polarity detection to hd-in 0: positive 1: negative detects the width from the hd-in pin to determine whether it is negative or not. when the high level of the input is wider than approx 13.5 us, hd-pol shows 1. vd-pol polarity detection to vd-in 0: positive 1: negative detects the width from the vd-in pin to determine whether it is negative or not. when the high level of the input is wider than approx 4.5 ms, vd-pol shows 1. h format horizontal format detection 0000: 15.625/15.75 khz 0001: 28.125 khz 0010: 31.25/31.5 khz 0011: 33.75 khz 0100: 37.5/37.9 khz 0101: 45/48 khz 0110: 56.25 khz 0111: 64/67.5 khz 1000: 75 khz 1001 to 1111: undefined detects a horizontal format (horizontal frequency). v format vertical format detection 000: 50 hz 001: 60 hz 010: 48 hz 011: 30 hz 100: 25 hz 101: 24 hz 110 to 111: undefined detects a vertical format (horizontal frequency) according to v freq det data. fb det1(2) voltage detection of fb pin for scart connector 0: not always high 1: always high detects the voltage of fb-in pin, selected by fb1(2) out (to pin 9 (22)) to determine whether the voltage is always high or not. sig det no-input detection. 0: no input 1: a signal detected the signal to the no-input detection circuit is selected by sig sw. refer to the relevant functions for h count max, h count min, sig det n, sig reset n, sig reset, sig det impe and sig det lvl.
TB1311AFG 2006-05-29 18 register name function hv-out format format detection result. h and v dummy output frequencies depend on this result. 00000: 15.625 khz, 50 hz (625i) 00001: 15.75 khz, 60 hz (525i) 00010: 31.25 khz, 50 hz (625p) 00011: 31.5 khz, 60 hz (525p, vga @60 hz) 00100: 28.125 khz, 50 hz (1125/50i) 00101: 33.75 khz, 60 hz (1125/60i) 00110: 37.5 khz, 50 hz (750/50p) 00111: 45 khz, 60 hz (750/60p, xga @60 hz) 01000: 31.25 khz, 50 hz (1250i) 01001: 37.9 khz, 60 hz (svga @60 hz) 01010: 64 khz, 60 hz (1125/60p, sxga @60 hz) 01011: 75 khz, 60 hz (uxga @60 hz) 01100: 56.25 khz, 50 hz (1125/50p) 01101 to 01111: not available 10000: 15.734 khz, 30 hz (525/30p) 10001: 27 khz, 24 hz (1125/24p) 10010: 28.125 khz, 25 hz (1125/25p) 10011: 33.75 khz, 30 hz (1125/30p) 10100: 27 khz, 48 hz (1125/24sf) 10101 to 11111: not available dc1 to 12 dc voltage detection for d-pin or s-pin 00: low (0 v) 01: mid (2.2 v) 10: undefined 11: high (5 v) remark 1: see below for the relationship between this function number and the pin number. dc1 - pin 39, dc2 - pin 40, dc3 - pin 44, dc4 - pin 46, dc5 - pin 48, dc6 - pin 50, dc7 - pin 60, dc8 - pin 64, dc9 - pin 66, dc10 - pin 68, dc11 - pin 70, dc12 - pin 80 remark 2; d-pin sw line: 00: connected 01: ---- 10: ---- 11: not connected line1: 00: 525 (480) 01: 750 (720) 10: ---- 11: 1125 (1080) line2: 00: interlace 01: ---- 10: ---- 11: progressive line3: 00: 4:3 01: 4:3 letter box 10: ---- 11: 16:9 remark 3; about s-pin 00: 4:3 01: 4:3 letter box 10: ---- 11: 16:9 s1 to 8 detects whether s-pin is connected or not. 0: low (not connected) 1: open (connected) remark 1: an external circuit is necessary to use this function. refer to the function description. remark 2: see below for the relationship between this function number and the pin number. s1 - pin 45, s2 - pin 47, s3 - pin 53, s4 - pin 59, s5 - pin 65, s6 - pin 67, s7 - pin 73, s8 - pin 79 v freq det counts the vertical frequency of an input selected by sync sw. when v-det = 0: 00000000: over 3.5 khz 01001111: 44 hz or less 01010000 to 11111111: no input when v-det = 1: 00000000: over 3.5 khz 10011001: 23 hz or less 10011010 to 11111111: no input how to calculate a vertical frequency (y): convert data read from v freq det into a decimal value and call it x. vertical frequency (y) = 1 (x 2.8607 10 -4 ) [hz] the error range of x is ? 1 to + 1. h freq det counts the horizontal frequency of an input selected by sync sw. when for sync-in; 00000001: no input 11111111: over 85 khz when for hd/vd-in; 00000000: no input 11111111: over 85 khz how to calculate a horizontal frequency (y): convert data read from h freq det into a decimal value and call it x. horizontal frequency (y) = 1 (0.003 x) [hz] the error range of x is ? 1 to + 1. note 1: in determining the decision algorithms (detection range, detection times, and so on) for h/v frequency detection, it is necessary to take into account both previously mentioned cautions and other factors such as signal conditions and i 2 cbus data transmission in the course of prototype tv set evaluation. note 2: the read bus flags indicate that a certain signal is detected at a given moment. however, the detection result will not be very reliable if only one flag is checked. to obtain accuracy, it is recommended that a judgment should be made on the basis of confirming several times and verifying agreement among the majority of flags read in a sequence and/or at the same time.
TB1311AFG 2006-05-29 19 function descriptions output selections outputs are switched by i2cbus registers, as in the following tables. ycbcr1 out register settings outputs available input y cbcr1 out cbcr pin4cbcr pin3 cbcr pin2 cbcr pin1 y1/g1 out (pin 6) cb1/b1 out (pin 8) cr1/r1 out (pin 10) cvbs yc ycbcr rgb 0000 ? ? ? ? mute mute mute 0001 ? ? ? ? sy1 (pin 57) sc1 (pin 59) mute y y 0010 ? ? ? ? sy2 (pin 77) sc2 (pin 79) mute y y 0011 ? ? ? ? cvbs3 (pin 36) mute mute y 0100 ? ? ? ? cvbs4 (pin 38) mute mute y ? ? ? 0 cvbs5 (pin 41) mute mute y 0101 ? ? ? 1 cvbs5 (pin 41) cr1 (pin 45) mute y y ? ? 0 ? cvbs6 (pin 61) mute mute y 0110 ? ? 1 ? cvbs6 (pin 61) cr2 (pin 65) mute y y ? ? ? 0 y1 (pin 49) cb1 (pin 47) cr1 (pin 45) y y y 0111 ? ? ? 1 y1 (pin 49) cb1 (pin 47) mute y y ? ? 0 ? y2 (pin 69) cb2 (pin 67) cr2 (pin 65) y y y 1000 ? ? 1 ? y2 (pin 69) cb2 (pin 67) mute y y ? 0 ? ? y3 (pin 55) cb3 (pin 53) cr3 (pin 51) y y y 1001 ? 1 ? ? y3 (pin 55) cb3 (pin 53) mute y y 0 ? ? ? y4 (pin 75) cb4 (pin 73) cr4 (pin 71) y y y 1010 1 ? ? ? y4 (pin 75) cb4 (pin 73) mute y y 1011 ? ? ? ? cr3 (pin 51) mute mute y 1100 ? ? ? ? cr4 (pin 71) mute mute y 1101 to 1111 ? ? ? ? not available ? : don?t care ycbcr2 out register settings outputs available input y cbcr1 out cbcr pin4 cbcr pin3cbcr pin2 cbcr pin1 y2/g2 out (pin 19) cb2/b2 out (pin 21) cr2/r2 out (pin 23) cvbs yc ycbcr rgb 0000 ? ? ? ? mute mute mute 0001 ? ? ? ? sy1 (pin 57) sc1 (pin 59) mute y y 0010 ? ? ? ? sy2 (pin 77) sc2 (pin 79) mute y y 0011 ? ? ? ? cvbs3 (pin 36) mute mute y 0100 ? ? ? ? cvbs4 (pin 38) mute mute y ? ? ? 0 cvbs5 (pin 41) mute mute y 0101 ? ? ? 1 cvbs5 (pin 41) cr1 (pin 45) mute y y ? ? 0 ? cvbs6 (pin 61) mute mute y 0110 ? ? 1 ? cvbs6 (pin 61) cr2 (pin 65) mute y y ? ? ? 0 y1 (pin 49) cb1 (pin 47) cr1 (pin 45) y y y 0111 ? ? ? 1 y1 (pin 49) cb1 (pin 47) mute y y ? ? 0 ? y2 (pin 69) cb2 (pin 67) cr2 (pin 65) y y y 1000 ? ? 1 ? y2 (pin 69) cb2 (pin 67) mute y y ? 0 ? ? y3 (pin 55) cb3 (pin 53) cr3 (pin 51) y y y 1001 ? 1 ? ? y3 (pin 55) cb3 (pin 53) mute y y 0 ? ? ? y4 (pin 75) cb4 (pin 73) cr4 (pin 71) y y y 1010 1 ? ? ? y4 (pin 75) cb4 (pin 73) mute y y 1011 ? ? ? ? cr3 (pin 51) mute mute y 1100 ? ? ? ? cr4 (pin 71) mute mute y 1101 to 1111 ? ? ? ? not available ? : don?t care
TB1311AFG 2006-05-29 20 monitor out register settings outputs available input mon out yc mix cbcr pin4 cbcr pin3 cbcr pin2 cbcr pin1 monitor out (pin 2) cvbs yc 0000 ? ? ? ? ? mute 0 sy1 (pin 57) y 0001 1 ? ? ? ? sy1 (pin 57) + sc1 (pin 59) y 0 sy2 (pin 77) y 0010 1 ? ? ? ? sy2 (pin 77) + sc2 (pin 79) y 0011 ? ? ? ? ? cvbs3 (pin 36) y 0100 ? ? ? ? ? cvbs4 (pin 38) y ? ? ? ? 0 cvbs5 (pin 41) y 0 cvbs5 (pin 41) y 0101 1 ? ? ? 1 cvbs5 (pin 41) + cr1 (pin 45) y ? ? ? 0 ? cvbs6 (pin 61) y 0 cvbs6 (pin 61) y 0110 1 ? ? 1 ? cvbs6 (pin 61) + cr2 (pin 65) y 0 y1 (pin 49) y 0111 1 ? ? ? ? y1 (pin 49) + cb1 (pin 47) y 0 y2 (pin 69) y 1000 1 ? ? ? ? y2 (pin 69) + cb2 (pin 67) y 0 y3 (pin 55) y 1001 1 ? ? ? ? y3 (pin 55) + cb3 (pin 53) y 0 y4 (pin 75) y 1010 1 ? ? ? ? y4 (pin 75) + cb4 (pin 73) y 1011 ? ? ? ? ? cr3 (pin 51) y 1100 ? ? ? ? ? cr4 (pin 71) y 1101 to 1111 ? ? ? ? ? not available ? : don?t care
TB1311AFG 2006-05-29 21 vertical sync separation for 1250i/50 when hv freq2 = 01000, the vertical sync separation for the 1250i/50 is accomplished through the use of a special circuit. the phase of the vd-out (pin 13) depends on the h-sync timing shown in the figure below. there is no vd-out when there is no h-sync input. in the manual sync processing mode (a-sync = off), use read bus functions, v-sync-w and h, v format (or h, v freq det) to detect the 1250i/50. note: the tailing edge of the vd-out has a jitter. use the leading edge only. hd width hd-out width is selectable by hd width as below. a setting in which hd width = 1 (narrow) is recommended for the 1125/50p/60p format owing to crosstalk from hd-out to video signals causing spike noise on video signals. sync-in (y-in) hd-out (hd width = 1) hd-out (hd width =0 ) 1.7 s (typ.) 0.7 s (typ.) 1125/60p signal hd/vd input amplitude when a 5.6 k ? is added before the input pin like the following figure, 5.0 vp-p pulse input is allowed. however, the acceptable minimum amplitude then becomes 2.0 vp-p. normal application for large-input application
TB1311AFG 2006-05-29 22 automatic sync processing mode (a-sync) counted horizontal and vertical frequency data to input signal are returned to read bus functions, h, v freq det. also, the detected format is returned to h, v format and h, v fm2 when the h/v frequencies are in internal defined ranges. input detection results for h, v-sync or hd,vd, which indicate whether or not input exists, are returned to h,v in. hv-out format indicates the active mode. in automatic sync processing mode (when a-sync = on), this device operates as indicated in the following table according to these read data. then, the sync1-in pin is not used for format detection. input condition hv-out format, h, v format status h, v fm2 status h, v in status hd, vd outputs standard format the format as input known signal the separated sync as input nonstandard format the status indicates not the current condition but the last detected format. unknown signal the separated sync as input no input the status indicates not the current condition but the last detected format. known: the status indicates not the current condition but the last detected format. no input dummy hd and vd, of which the frequency depends on the hv-out format status note 3: dummy hd and vd may become unstable while the mode is changing from one format to another. manual sync processing mode (a-sync = off) in this mode, the sync1-in pin is used only for detecting the input format and the sync2-in pin is used only for separating h and v syncs for hd and vd outputs. it is possible to detect some input formats by means of time-sharing while separating syncs to another input. the following is an example of how to detect h/v frequency when a-sync = off. 1. input the signal from yvi-out pin into the sync1-in pin. 2. read data such as h, v freq det and h, v format. 3. detect the h/v frequency by microprocessor or similar means, depending on the data obtained. 4. input the detected signal into the sync2-in pin and set hv freq2 and so on for the sync2-in pin to the detected mode. 5. continue to monitor the obtained data for the sync1-in pin, such as h, v freq det and h, v format. when any alterations are recognized, re-set hv freq2 and so on for the sync2-in pin. decision algorithms (for detection range, detection times and so on) for h/v frequency detection should be determined taking into account the above-mentioned errors in measuring h/v frequencies and other factors such as signal conditions and i 2 cbus data transmission in the course of prototype tv set evaluation. by the way, in a-sync = off and h, v dmy = on mode, dummy hd and vd are output according to the hv freq2 setting when there is no input. i2cbus i2cbus fig. signal route when a-sync = on fig. signal route when a-sync = off
TB1311AFG 2006-05-29 23 sync separation level the sync separation level is changed according to the ratio of h-sync width to one line. typical sync separation levels for each format are as follows. hv-sep data 00 01 10 11 625/50i 18 26 31 43 525/60i 18 26 31 43 625/50p 19 27 32 44 525/60p 19 27 32 44 1125/50i 27 34 40 52 1125/60i 25 33 38 50 750/50p 25 32 38 50 750/60p 24 31 36 49 1250/50i 22 30 36 48 1125/50p 28 36 41 52 1125/60p 27 34 39 52 525/30p 18 26 31 43 1125/24p 27 34 40 52 1125/25p 27 34 40 52 1125/30p 26 32 38 50 1125/24sf 28 34 40 52 vga/60 20 26 32 43 svga/60 20 27 33 44 xga/60 20 27 33 44 sxga/60 22 29 34 45 expressed as percentages, where 286 mvp-p sync applies to 525/60i and 300 mvp-p sync applies otherwise the format detection and sync separation performances are c hanged due to the separation level set by hv-sep setting and the connected coupling capacitor value. the careful evaluations are required to set the separation level under consideration of expected input conditions such as a suppressed sync input, an input with v-sag, and apl (average picture level) fluctuations. for ?sync on g? signal, hd-out is not output during the v-sync period because there is no h-sync during the v-sync period. (note) cross-talk from hd, vd, fb or sync-in to video-outs the edges of hd/vd/fb-out leaks into video-outs when hd-out, vd-out and/or fb-out is output. if the video-out is not synchronized with the hd/vd/fb-out, (e.g. desynchronized videos between main- and sub-picture like pinp or double window), the edges looks as desynchronized noise. the crosstalk level will be improved when the bandwidth frequency will be set to higher. please use this device under consideration of the cross-talk.
TB1311AFG 2006-05-29 24 no-input detection this function detects whether there is input or not. it is useful for detecting no-input of 525i or 625i even if which is a weakened signal strength. (1)0 (no-input) ? 1 (detected) when nmin Q n1 Q nmax, and when n2 R ndet, sig det returns 1. where, nmin: the number set by h count min nmax: the number set by h count max ndet: the number set by sig det n n1: the number of the h-sync count in the counter during an internal window (approx. 2 ms) n2: the number of conditions that ?nmin Q n1 Q nmax? is detected (2) 1 (detected) ? 0 (no-input) when n1 Q nmin, n1 R nmax, and when n3 R nreset, sig det returns 0. where, nreset: the number set by sig reset n n3: the number of conditions that ?n1 Q nmin and n1 R nmax? is detected ext. cap. sync filter pin fig. block diagram for no-input detection decide how to use no-input detection after making a thorough evaluation using a prototype tv set.
TB1311AFG 2006-05-29 25 s-pin insertion detection c-in pins detect the dc level to determine whether the s-pin is inserted or not. fig. application of s-pin insertion detection audio gain audio gain is controlled by au1(2) att. the following figure shows the typical characteristic, where the series-connected resistor is 5.6 k ? . -100 -80 -60 -40 -20 0 20 0 20 40 60 80 100 120 au1(2) att data attenuation [db] 127
TB1311AFG 2006-05-29 26 typical characteristics 0 0 1 10 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 input [vrms] total harmonic distortion [%] fixed mode (au fix = 0) att mode (au fix = 1, au att = max) 0.1 0.01 fig. audio total harmonic distortion (input resistance: 5.6 k ? ) -50 -40 -30 -20 -10 0 10 0.1 1 10 100 frequency [mhz] gain [db] f0 sw = low, bandwidth = min, fc half = on f0 sw = low, bandwidth = min f0 sw = high, bandwidth = min f0 sw = high, bandwidth = max fig. typical prefilter frequency characteristics
TB1311AFG 2006-05-29 27 0 10 20 30 40 50 0 20406080100120 bandwidth data cutoff frequency (-3 db point) [mhz] fo sw = high fo sw = low fo sw = high, fc half = on fo sw = low, fc half = on 127 fig. typical cutoff frequency (-3 db point) characteristics of prefilter 0 50 100 150 200 250 0 20406080100120 bandwidth data delay time [ns] fo sw = high fo sw = low fo sw = high, fc half = on fo sw = low, fc half = on 127 fig. typical delay-time (group delay @ 1 mhz) characteristics of prefilter recommended crystal oscillator when a connected crystal oscillator is used for the xo, the following oscillation specifications are required. oscillation frequency (fundamental): 3.579545 mhz (for ntsc decoding) frequency tolerance: +/- 50 ppm external cw input into crystal oscillator pin instead of connecting a crystal oscillator, it is possible to input an external cw (continual wave) into pin 28 through a capacitor as below. the required specs on the cw are as follows. input frequency (fundamental): 3.579545 mhz +/- 50 ppm input amplitude: 1.0vp-p +/- 0.5vp-p
TB1311AFG 2006-05-29 28 how to deal with unused pins unused pins should be dealt with as below. pins not mentioned below should be connected properly. pin no. pin name procedure pin no. pin name procedure 1 al3 out procedure 3 46 ar9 in/dc4 procedure 1 2 monitor out procedure 3 47 cb1/b1 in procedure 1 3 ar3 out procedure 3 48 al9 in/dc5 procedure 1 4 cvbs1 out procedure 3 49 y1/g1 in procedure 1 5 al1 out procedure 3 50 fb3 in/dc6 procedure 2 6 y1/g1 out procedure 3 51 cr3/r3 in procedure 1 7 ar1 out procedure 3 52 ar3 in procedure 1 8 cb1/b1 out procedure 3 53 cb3/b3-in procedure 1 9 fb1 out procedure 3 54 al3 in procedure 1 10 cr1/r1 out procedure 3 55 y3/g3 in procedure 1 12 hd out procedure 3 56 ar4 in procedure 1 13 vd out procedure 3 57 sy1 in procedure 1 14 sync filter procedure 3 58 al4 in procedure 1 15 sync2 in procedure 1 59 sc1 in procedure 1 17 cvbs2 out procedure 3 60 dc7 procedure 2 18 al2 out procedure 3 61 cvbs6 in procedure 1 19 y2/g2 out procedure 3 62 ar5 in procedure 1 20 ar2 out procedure 3 63 al5 in procedure 1 21 cb2/b2 out procedure 3 64 fb2 in/dc8 procedure 2 22 fb2 out procedure 3 65 cr2/r2 in procedure 1 23 cr2/r2 out procedure 3 66 ar10 in/dc9 procedure 1 30 vd in procedure 4 67 cb2/b2 in procedure 1 31 hd in procedure 4 68 al10 in/dc10 procedure 1 33 sync1 in procedure 1 69 y2/g2 in procedure 1 34 yvi out procedure 3 70 fb4 in/dc11 procedure 2 35 ar1 in procedure 1 71 cr4/r4 in procedure 1 36 cvbs3 in procedure 1 72 ar6 in procedure 1 37 al1 in procedure 1 73 cb4/b4-in procedure 1 38 cvbs4 in procedure 1 74 al6 in procedure 1 39 ar8 in/dc1 procedure 1 75 y4/g4 in procedure 1 40 al8 in/dc2 procedure 1 76 ar7 in procedure 1 41 cvbs5 in procedure 1 77 sy2 in procedure 1 42 ar2 in procedure 1 78 al7 in procedure 1 43 al2 in procedure 1 79 sc2 in procedure 1 44 fb1 in/dc3 procedure 2 80 dc12 procedure 2 45 cr1/r1 in procedure 1 ? ? ? procedure 1: connect a 0.01 f capacitor between this pin and gnd. procedure 2: connect to gnd. procedure 3: leave open. procedure 4: connect a 10 k ? resistor between this pin and gnd.
TB1311AFG 2006-05-29 29 how to start the i 2 cbus after power on, send bus data as follows. use software to handle the procedure. 1. turn on the power. 2. transmit all the write data. how to transmit/receive via the i 2 cbus slave address: de h / df h a6 a5 a4 a3 a2 a1 a0 w/r 1 1 0 1 1 1 1 0/1 start and stop conditions bit transmission acknowledgement sda from transmitter low impedance at bit 9 only clock pulse for acknowledgement s high impedance at bit 9 1 8 9 sda from receiver scl from master sda scl s start condition p stop condition sda scl sda must not be changed sda may be changed
TB1311AFG 2006-05-29 30 data transmit format 1 data transmit format 2 data receive format to receive data, the master transmitter changes to a receiver immediately after the first acknowledgement. the slave receiver changes to a transmitter. the end condition is always created by the master. optional data transmit format (automatic increment mode) in this way, sub-addresses are automatically incremented from the specified sub-address and data are set. i 2 cbus conditions parameter symbol min typ. max unit low level input voltage v il 0 ? 1.1 v high level input voltage v ih 2.4 ? v/s-vcc v hysteresis of schmitt trigger inputs v hys ? 0.7 ? v low level output voltage at 3 ma sink current v ol1 0 ? 0.4 v input current each i/o pin with an input voltage between 0.1 vdd and 0.9 vdd i i -10 ? 10 a capacitance for each i/o pin c i ? ? 10 pf scl clock frequency f scl 0 ? 400 khz hold time start condition t hd;sta 0.6 ? ? s low period of scl clock t low 1.3 ? ? s high period of scl clock t high 0.6 ? ? s set-up time for a repeated start condition t su;sta 0.6 ? ? s data hold time t hd;dat 0 ? ? ns data set-up time t su;dat 100 ? ? ns set-up time for stop condition t su;sto 0.6 ? ? s bus free time between a stop and start condition t buf 1.3 ? ? s note: this parameter is not tested during production and is provided only as information to assist the design of applications. s slave address 0 a transmit data 1 a sub-address a transmit data n a sub-address a p ?????? ?????? s slave address 0 a transmit data a sub-address a p 7-bit msb s: start condition 8-bit msb a: acknowledgement 8-bit msb p: end condition s slave address 1 a receive data n receive data 1 a p 7-bit msb 8-bit msb msb ????????? s slave address a transmit data n ???? transmit data 1 a p 7-bit msb 8-bit msb 0 sub-address 7-bit msb a 1 8-bit msb
TB1311AFG 2006-05-29 31 absolute maximum ratings (ta = 25c) characteristic symbol rating unit 9 v vcc v ccmax9 12.0 5 v vcc v ccmax5 6.0 supply voltage 3.3 v vcc v ccmax3 6.0 v input pin voltage v in gnd ? 0.3 to vcc + 0.3 v y or sync input amplitude (pin 15, 33, 36, 38, 41, 49, 51, 55, 57, 61, 69, 71, 75, 77) y in 2.0 vp-p power dissipation p d (note 4) 2451 mw power dissipation reduction rate 1/ ja 19.6 mw/ c operating temperature t opr ? 20 to 75 c storage temperature t stg ? 55 to 150 c note 4: refer to the figure below. note, however, that the condition applies only where the device is mounted on a board 114.3 x 76.2 x t:1.6 mm, cu 20%. mount the devive on a board which is larger than it. note 5: install the product correctly. otherwise, it may result in break down, damage and/or degration to the product or equipment. the absolute maximum ratings of a semiconductor device are a set of specified parameter values, which must not be exceeded during operation, even for an instant. if any of these rating would be exceeded during operation, the device electrical characteristics may be irreparably altered and the reliability and lifetime of the device can no longer be guaranteed. moreover, these operations with exceeded ratings may cause break down, damage and/or degradation to any other equipment. applications us ing the device should be designed such that eac h maximum rating will never be exceeded in any operating conditions. before using, creating and/or producing designs, refer to and comply with the precautions and conditions set forth in this documents. ambient temperature ta (c) power consumption reduction ratio p d (mw) 0 150 25 75 0 1471 2451 figure p d - ta curve
TB1311AFG 2006-05-29 32 operating conditions characteristic description min typ. max unit pin 24 8.5 9.0 9.5 pin 11 4.7 5.0 5.3 supply voltage (v cc ) pin 29; supply power from v/s vcc (pin 11) via a resistor. 3.1 3.3 3.5 v y/g signal input amplitude pins 49, 55, 69, 75; with sync ? 1.0 ? v p-p cvbs/sy input amplitude pins 36, 38, 41, 49, 55, 57, 61, 69, 75, 77 (51, 71); with sync ? 1.0 ? v p-p y/g signal input frequency pins 49, 55, 69, 75 0 ? 60 mhz cvbs/sy input frequency pins 36, 38, 41, 49, 55, 57, 61, 69, 75, 77 (51, 71) 0 ? 8 mhz sc (chroma) signal input amplitude pin 59, 79 (45, 47, 53, 65, 67, 73) ? ? 2 v p-p cb, cr, pb, pr signal input amplitude pins 45, 47, 51, 53, 65, 67, 71, 73; 100% color bar signal ? 0.7 ? v p-p cb, cr, pb, pr signal input frequency pins 45, 47, 51, 53, 65, 67, 71, 73 0 ? 60 mhz r, g, b signal input amplitude pins 45, 47, 49, 51, 53, 55, 65, 67, 69, 71, 73, 75; 100% white signal without sync ? 0.7 ? v p-p r, g, b signal input frequency pins 45, 47, 49, 51, 53, 55, 65, 67, 69, 71, 73, 75 0 ? 60 mhz hd, vd signal input amplitude pins 30, 31 1.0 ? 2.0 v p-p hd input frequency pins 31 for freq counter 0 ? 85 khz vd input frequency pins 30 for freq counter 23 ? 3500 hz h 1.0 ? 3.0 fb input level pins 44, 50, 64, 70 l gnd ? 0.4 v fb input width pins 44, 50, 64, 70 80 ? ? ns h 3.5 ? v/s vcc m 1.4 2.2 2.4 dc1 to 12 pins 39, 40, 44, 46, 48, 50, 60, 64, 66, 68, 70, 80 l gnd ? 0.6 v dc detection input voltage s1 to 8 pins 45, 47, 53, 59, 65, 67, 73, 79 l gnd ? 0.6 v sda input current pins 25 ? ? 3 ma remark: supply power to all vcc pins (pin 11, 24, 29).
TB1311AFG 2006-05-29 33 electrical characteristics (unless otherwise specified, au v cc = 9 v, v/s v cc = 5 v, v dd = 3.3 v, ta = 25c, i 2 cbus data: preset values) current consumption (au8/9/10 pin = 1, f0 sw1/2 = 1, bandwidth1/2 = max) pin name symbol test conditions min typ. max unit au v cc (pin 24) i ccau ? 7.5 9.5 12.5 v/s v cc (pin 11) i ccvs ? 100 125 165 v dd (pin 29) i ccd resistance to 5 v; r = 180 ? 6.3 9.4 12.8 ma pin voltage (test condition: no signal input) pin no. pin name symbol test conditions min typ. max unit 1 al3 out v 1 ? 3.8 4.1 4.4 2 monitor out v 2 ? 0.9 1.2 1.5 3 ar3 out v 3 ? 3.8 4.1 4.4 4 cvbs1 out v 4 ? 1.0 1.3 1.6 5 al1 out v 5 ? 3.8 4.1 4.4 6 y1/g1 out v 6 ? 1.0 1.3 1.6 7 ar1 out v 7 ? 3.8 4.1 4.4 8 cb1/b1 out v 8 ? 1.0 1.3 1.6 10 cr1/r1 out v 10 ? 1.0 1.3 1.6 14 sync filter v 14 ? 3.0 3.3 3.6 15 sync2 in v 15 ? 1.5 1.8 2.1 17 cvbs2 out v 17 ? 1.0 1.3 1.6 18 al2 out v 18 ? 3.8 4.1 4.4 19 y2/g2 out v 19 ? 1.0 1.3 1.6 20 ar2 out v 20 ? 3.8 4.1 4.4 21 cb2/b2 out v 21 ? 1.0 1.3 1.6 23 cr2/r2 out v 23 ? 1.0 1.3 1.6 28 xtal v 28 ? 3.8 4.05 4.3 30 vd in v 30 ? 1.2 1.45 1.7 31 hd in v 31 ? 1.2 1.45 1.7 33 sync1 in v 33 ? 1.5 1.8 2.1 34 yvi out v 34 ? 1.9 2.2 2.5 35 ar1 in v 35 ? 4.2 4.4 4.6 36 cvbs3 in v 36 ? 2.0 2.3 2.6 37 al1 in v 37 ? 4.2 4.4 4.6 38 cvbs4 in v 38 ? 2.0 2.3 2.6 39 ar8 in/dc1 v 39 ? 4.2 4.4 4.6 40 al8 in/dc2 v 40 ? 4.2 4.4 4.6 v
TB1311AFG 2006-05-29 34 pin no. pin name symbol test conditions min typ. max unit 41 cvbs5 in v 41 ? 2.0 2.3 2.6 42 ar2 in v 42 ? 4.2 4.4 4.6 43 al2 in v 43 ? 4.2 4.4 4.6 45 cr1/r1 in v 45 ? 2.6 2.9 3.2 46 ar9 in/dc4 v 46 ? 4.2 4.4 4.6 47 cb1/b1 in v 47 ? 2.6 2.9 3.2 48 al9 in/dc5 v 48 ? 4.2 4.4 4.6 49 y1/g1 in v 49 ? 2.0 2.3 2.6 51 cr3/r3 in v 51 ? 2.6 2.9 3.2 52 ar3 in v 52 ? 4.2 4.4 4.6 53 cb3/b3 in v 53 ? 2.6 2.9 3.2 54 al3 in v 54 ? 4.2 4.4 4.6 55 y3/g3 in v 55 ? 2.0 2.3 2.6 56 ar4 in v 56 ? 4.2 4.4 4.6 57 sy1 in v 57 ? 2.0 2.3 2.6 58 al4 in v 58 ? 4.2 4.4 4.6 59 sc1 in v 59 ? 2.6 2.9 3.2 61 cvbs6 in v 61 ? 2.0 2.3 2.6 62 ar5 in v 62 ? 4.2 4.4 4.6 63 al5 in v 63 ? 4.2 4.4 4.6 65 cr2/r2 in v 65 ? 2.6 2.9 3.2 66 ar10 in/dc9 v 66 ? 4.2 4.4 4.6 67 cb2/b2 in v 67 ? 2.6 2.9 3.2 68 al10 in/dc10 v 68 ? 4.2 4.4 4.6 69 y2/g2 in v 69 ? 2.0 2.3 2.6 71 cr4/r4 in v 71 ? 2.6 2.9 3.2 72 ar6 in v 72 ? 4.2 4.4 4.6 73 cb4/b4 in v 73 ? 2.6 2.9 3.2 74 al6 in v 74 ? 4.2 4.4 4.6 75 y4/g4 in v 75 ? 2.0 2.3 2.6 76 ar7 in v 76 ? 4.2 4.4 4.6 77 sy2 in v 77 ? 2.0 2.3 2.6 78 al7 in v 78 ? 4.2 4.4 4.6 79 sc2 in v 79 ? 2.6 2.9 3.2 v
TB1311AFG 2006-05-29 35 audio block characteristic symbol test conditions min typ max unit i/o gain for fixed mode (al/ar1, al/ar2, al/ar3) gauf -1.0 0 1.0 au att = min gaumin ? -90 -80 i/o gain for att mode (al/ar1, al/ar2) au att = max gaumax input = 2.8 vp-p, 1 khz, input resistance 5.6 k ? 0 1.0 2.0 db i/o frequency characteristic fau -3 db point, note a 100 ? ? khz total harmonic distortion fixed mode (al/ar1, al/ar2, al/ar3) thdf ? 0.02 0.05 total harmonic distortion for att mode (al/ar1, al/ar2) au att = max thdmax input = 2.8 vp-p 1 khz, note a ? 0.1 0.3 % input dynamic range vdyau note a, note b 5.6 6.5 ? vp-p output offset voltage vauswof offset on au1(2,3) out between au1(2,3) out = 0000 to 1010 -30 0 30 mv att control offset vattof offset on au1(2) out between au1(2) att = max to min -100 0 100 mv ripple rejection ratio vrrr 100 hz and 100 mvp-p ripple is added to au vcc, note a 30 45 ? db mute mode attenuation gaumute input = 2.8vp-p, 1 khz, note a 75 85 ? db crosstalk among inputs gaucrs input = 2.8vp-p, 1 khz, note a 75 85 ? db s/n ratio gausn input = 2.8vp-p, 1 khz, note a 80 90 ? db imau1 pins 35, 37, 42, 43, 52, 54, 56, 58, 62, 63, 72, 74, 76, 78 65 87 109 imau2 au8/9/10 = 1 (audio input mode), pins 39, 40, 46, 48, 66, 68 65 87 109 input impedance of input pins imaudc au8/9/10 = 0 (dc input mode), pins 39, 40, 46, 48, 66, 68 122 163 204 k ? note a: this parameter is not tested during production and is provided only as information to assist the design of applications . note b: input = 1 khz. the amplitude when the total harmonic distortion becomes 1%. video block characteristic symbol test conditions min typ. max unit sync-tip clamp mode vdsync 1.5 1.7 ? bias mode vdbias 1.4 2.1 ? input dynamic range monitor out vdmoni filpass = 0, bandwidth = max, sine wave input for bias mode, y with sync for others. 1.35 1.5 ? vp-p gain = -3 db g-3 -3.5 -3.0 -2.5 gain = 0 db g0 -0.5 0 0.5 gain = +3 db g+3 cvbs-out, ycbcr-out filpass = 0/1, input = 0.2vp-p 10 khz, bandwidth = cnt, f0 sw = 1 2.5 3.0 3.5 gain = +6 db g+6 monitor out 5.5 6.0 6.5 i/o gain yvi-out gyvi yvi-out -0.5 0 0.5 db gycmy sy-in to monitor-out, no input into sc-in, yc mix = 1 5.5 6.0 6.5 yc mix gain gycmc sc-in to monitor-out, no input into sy-in, yc mix = 1 5.5 6.0 6.5 db
TB1311AFG 2006-05-29 36 characteristic symbol test conditions min typ. max unit ycbcr gain = -3 db fg-3 80 100 ? ycbcr gain = 0 db fg0 80 100 ? i/o frequency characteristic 1-1 (ycbcr) ycbcr gain = +3 db fg+3 filpass = 1, 0.2 vp-p input, -3 db point, note a 80 100 ? mhz bandwidth = max flmax 14.0 16.5 18.0 bandwidth = cnt flcnt 9.5 10.5 11.5 i/o frequency characteristic 1-2 (ycbcr) bandwidth = min flmin filpass = 0, gain = 00, f0 sw = 0, 0.2 vp-p input, -3 db point, note a 4.2 4.7 5.2 mhz bandwidth = max fhmax 41 46 51 bandwidth = cnt fhcnt 27 30.3 34 i/o frequency characteristic 1-3 (ycbcr) bandwidth = min fhmin filpass = 0, gain = 00, f0 sw = 1, 0.2 vp-p input, -3 db point, note a 12 13.4 15 mhz bandwidth = max fhflmax 7.4 8.3 9.1 bandwidth = cnt fhflcnt 4.6 5.2 5.8 i/o frequency characteristic 1-4 (cbcr) bandwidth = min fhflmin filpass = 0, gain = 00, f0 sw = 0, fc half = 1, -3 db point, note a 2.1 2.4 2.6 mhz bandwidth = max fhfhmax 21 24.1 27 bandwidth = cnt fhfhcnt 14 15.7 18 i/o frequency characteristic 1-5 (cbcr) bandwidth = min fhfhmin filpass = 0, gain = 00, f0 sw = 1, fc half = 1, 0.2 vp-p input, -3 db point, note a 6.0 6.8 8.0 mhz ycbcr gain = -3 db fdg-3 ? 0 ? ycbcr gain = 0 db fdg0 ? 0 ? differential 1-1 of frequency characteristic among ycbcr outputs ycbcr gain = +3 db fdg+3 filpass = 1, 0.2 vp-p input, -3 db point, note a ? 0 ? mhz bandwidth = max fdhmax -0.90 0 0.90 bandwidth = cnt fdlcnt -0.5 0 0.5 differential 1-2 of frequency characteristic among ycbcr outputs bandwidth = min fdhmin filpass = 0, f0 sw = 0, 0.2 vp-p input, -3 db point, note a -0.23 0 0.23 mhz bandwidth = max fdhmax -3.2 0 3.2 bandwidth = cnt fdhcnt -1.05 0 1.05 differential 1-3 of frequency characteristic among ycbcr outputs bandwidth = min fdhmin filpass = 0, f0 sw = 1, 0.2 vp-p input, -3 db point, note a -0.70 0 0.70 mhz ycbcr gain = -3 db tdl-3 ? 4 10 ycbcr gain = 0 db tdl0 ? 4 10 i/o delay time 1-1 (ycbcr) ycbcr gain = +3 db tdl+3 filpass = 1, 1 mhz, note a ? 4 10 ns bandwidth = max tdlmax 28 33 38 bandwidth = cnt tdlcnt 45 48 55 i/o delay time 1-2 (ycbcr) bandwidth = min tdlmin filpass = 0, gain = 00, f0 sw = 0, 1 mhz, note a 96 107 120 ns bandwidth = max tdhmax 10 16 20 bandwidth = cnt tdhcnt 15 20 25 i/o delay time 1-3 (ycbcr) bandwidth = min tdhmin filpass = 0, gain = 00, f0 sw = 1, 1 mhz, note a 35 39 45 ns
TB1311AFG 2006-05-29 37 characteristic symbol test conditions min typ. max unit bandwidth = max tdhflmax 55 60 65 bandwidth = cnt tdhflcnt 80 91 100 i/o delay time 1-4 (cbcr) bandwidth = min tdhflmin filpass = 0, gain = 00, f0 sw = 0, fc half = 1, 1 mhz, note a 190 220 260 ns bandwidth = max tdhfhmax 20 24 30 bandwidth = cnt tdhfhcnt 29 34 39 i/o delay time 1-5 (cbcr) bandwidth = min tdhfhmin filpass = 0, gain = 00, f0 sw = 1, fc half = 1, 1 mhz, note a 66 72 80 ns ycbcr gain = -3 db tddg-3 -10 0 10 ycbcr gain = 0 db tddg0 -10 0 10 differential 1-1 of delay time among ycbcr outputs ycbcr gain = +3 db tddg+3 filpass = 1, 1 mhz, note a -10 0 10 ns bandwidth = max tddhmax -10 0 10 bandwidth = cnt tddhcnt -10 0 10 differential 1-2 of delay time among ycbcr outputs bandwidth = min tddhmin filpass = 0, f0 sw = 0, 1 mhz, note a -10 0 10 ns bandwidth = max tddhmax 0 8 20 bandwidth = cnt tddhcnt 5 14 20 differential 1-3 of delay time between y and cb/cr outputs bandwidth = min tddhmin filpass = 0, f0 sw = 1, fc half = 1, 1 mhz, note a 25 33 45 ns bandwidth = max tddhmax -10 0 10 bandwidth = cnt tddhcnt -10 0 10 differential 1-4 of delay time between cb and cr outputs bandwidth = min tddhmin filpass = 0, f0 sw = 0, fc half = 1, 1 mhz, note a -20 0 20 ns cvbs gain = -3 db fg-3c 60 80 ? cvbs gain = 0 db fg0c 60 80 ? i/o frequency characteristic 2-1 (cvbs) cvbs gain = +3 db fg+3c filpass = 1, 0.2 vp-p input, -3 db point, note a 60 80 ? mhz bandwidth = max fmaxc 14.0 16.4 18.0 bandwidth = cnt fcntc 9.5 10.6 11.5 i/o frequency characteristic 2-2 (cvbs) bandwidth = min fminc filpass = 0, gain = 00, 0.2 vp-p input, -3 db point, note a 4.1 4.6 4.9 mhz cvbs gain = -3 db tdl-3 ? 5 10 cvbs gain = 0 db tdl0 ? 5 10 i/o delay time 2-1 (cvbs) cvbs gain = +3 db tdl+3 filpass = 1, 1 mhz, note a ? 5 10 ns bandwidth = max tdmaxc 30 34 40 bandwidth = cnt tdcntc 45 49 55 i/o delay time 2-2 (cvbs) bandwidth = min tdminc filpass = 0, gain = 00, 1 mhz, note a 100 108 120 ns i/o frequency characteristic 3 (monitor) fgm 0.2 vp-p input, -3 db point, note a 60 80 ? mhz i/o frequency characteristic 4 (yvi) fgm 0.2 vp-p input, -3 db point, note a 80 100 ? mhz mute mode attenuation gmute 5 mhz sin wave input, note a ? -70 -60 db among input channels gcrschs ? -70 -60 among inputs in a channel gcrsins 5 mhz sin wave input, note a ? -60 -55 db crosstalk hd, vd, fb or sync-in to video-outs gcrsync while hd, vd or fb-out is output. bandwidth=min, note a ? 3 ? mv
TB1311AFG 2006-05-29 38 synchronization block (test condition: a-sync = 1 (on)) characteristic symbol test conditions min typ max unit vsep100 hv-sep = 00, note a, note c 12 18 24 vsep101 hv-sep = 01, note a, note c 20 26 32 vsep110 hv-sep = 10, note a, note c 26 31 38 525/60i vsep111 hv-sep = 11, note a, note c 38 43 50 % vsep200 hv-sep = 00, note a, note c 20 25 30 vsep201 hv-sep = 01, note a, note c 28 33 38 vsep210 hv-sep = 10, note a, note c 33 38 43 1125/60i vsep211 hv-sep = 11, note a, note c 45 50 55 % vsep300 hv-sep = 00, note a, note c 14 20 26 vsep301 hv-sep = 01, note a, note c 21 27 33 vsep310 hv-sep = 10, note a, note c 27 33 39 h/v-sync separation level svga/60 vsep311 hv-sep = 11, note a, note c 38 44 50 % threshold amplitude for hd input vthhd hv out = 1 0.8 ? ? vp-p threshold amplitude for vd input vthvdn hv out = 1 0.9 ? ? vp-p vhdh high level 1.0 1.2 1.4 hd-out voltage vhdl low level ? 0.1 0.4 v thdw0 hd width = 0 1.6 1.7 1.8 hd-out width thdw1 hd width = 1 0.6 0.7 0.8 s h sync-in to hd-out thdp1 hv out = 0, 1125/60p input, note d 70 90 110 ns hd-out phase hd-in to hd-out thdp2 hv out = 1, note a 25 34 40 ns vvdh high level 1.0 1.2 1.4 vd-out voltage vvdl low level ? 0.1 0.4 v sync sep tvdws separated vd-out ? 290 ? s 1250i odd tvdwodd ? 285 ? 1250i even tvdweven when 1250i input ? 270 ? s free-run 1 tvdwfi free-run vd-out in interlace mode ? 4 ? vd-out width free-run 2 tvdwfp free-run vd-out in progressive mode ? 8 ? h v sync-in to vd-out tvdp except 1250/50i input, note d 0.15 0.20 0.25 h h sync-in to vd-out tvdp1250 1250/50i input, h sync-in to vd-out, note d 310 320 330 ns vd-out phase vd-in to vd-out tvdphv hv out = 1, note a 25 34 40 ns note c: 286 mvp-p sync input for 525/60i, 0.3 vp-p sync input for 1125/60i and svga/60. note d: see the figures below.
TB1311AFG 2006-05-29 39 characteristic symbol test conditions min typ. max unit fh156 hv freq2 = 00000, h dmy = 1 ? 15.564 ? fh157/60i hv freq2 = 00001, h dmy = 1 ? 15.701 ? fh312 hv freq2 = 00010, h dmy = 1 ? 31.401 ? fh315 hv freq2 = 00011, h dmy = 1 ? 31.401 ? fh281/50i hv freq2 = 00100, h dmy = 1 ? 27.966 ? fh337/60i hv freq2 = 00101, h dmy = 1 ? 33.771 ? fh375 hv freq2 = 00110, h dmy = 1 ? 37.288 ? fh450 hv freq2 = 00111, h dmy = 1 ? 44.746 ? fh1250 hv freq2 = 01000, h dmy = 1 ? 31.401 ? fh379 hv freq2 = 01001, h dmy = 1 ? 37.288 ? fh640 hv freq2 = 01010, h dmy = 1 ? 66.288 ? fh750 hv freq2 = 01011, h dmy = 1 ? 74.577 ? fh562 hv freq2 = 01100, h dmy = 1 ? 55.932 ? fh157/30p hv freq2 = 10000, h dmy = 1 ? 15.700 ? fh270 hv freq2 = 10001, h dmy = 1 ? 27.117 ? fh281/25p hv freq2 = 10010, h dmy = 1 ? 27.965 ? fh337/30p hv freq2 = 10011, h dmy = 1 ? 33.769 ? dummy hd-out frequency fh270/48sf hv freq2 = 10100, h dmy = 1 ? 27.117 ? khz fv625i hv freq2 = 00000, v dmy = 1 ? 312.5 ? fv525i hv freq2 = 00001, v dmy = 1 ? 262.5 ? fv625p hv freq2 = 00010, v dmy = 1 ? 625 ? fv525p hv freq2 = 00011, v dmy = 1 ? 525 ? fv1125i50 hv freq2 = 00100, v dmy = 1 ? 562.5 ? fv1125i60 hv freq2 = 00101, v dmy = 1 ? 562.5 ? fv750p50 hv freq2 = 00110, v dmy = 1 ? 750 ? fv750p60 hv freq2 = 00111, v dmy = 1 ? 750 ? fv1250io hv freq2 = 01000, v dmy = 1, odd ? 624.5 ? fv1250ie hv freq2 = 01000, v dmy = 1, even ? 625.5 ? fvsvga hv freq2 = 01001, v dmy = 1 ? 628 ? fvsxga hv freq2 = 01010, v dmy = 1 ? 1066 ? fvuxga hv freq2 = 01011, v dmy = 1 ? 1250 ? fv1125p50 hv freq2 = 01100, v dmy = 1 ? 1125 ? fv525p30 hv freq2 = 10000, v dmy = 1 ? 525 ? fv1125p24 hv freq2 = 10001, v dmy = 1 ? 1125 ? fv1125p25 hv freq2 = 10010, v dmy = 1 ? 1125 ? fv1125p30 hv freq2 = 10011, v dmy = 1 ? 1125 ? dummy vd-out frequency fv1125s24 hv freq2 = 10100, v dmy = 1 ? 562.5 ? h
TB1311AFG 2006-05-29 40 other blocks characteristic symbol test conditions min typ. max unit xtal oscillation amplitude vosc note a, note e ? 0.4 ? vp-p fb input threshold voltage vthfb pins 44, 50, 64, 70 0.6 0.75 0.9 v vfbh high level 1.0 1.2 1.4 fb-out voltage vfbl low level ? 0.1 0.4 v dl off tfbdoff fb dl = 0 20 40 60 i/o delay time for fb dl on tfbdon fb dl = 1 50 70 90 ns no signal detection filter tnsfil1 sig lpf = 1, note f, note a 0.5 1.3 1.8 s imnsfil200 sig det impe = 00, note g 14 20 26 imnsfil201 sig det impe = 01, note g 11 15 19 imnsfil210 sig det impe = 10, note g 7 10 13 impedance for no-signal detection filter imnsfil211 sig det impe = 11, note g 4.2 6.0 7.8 k ? vthns00 sig det lvl = 00, note h 0.45 0.55 0.65 vthns01 sig det lvl = 01, note h 0.70 0.80 0.90 vthns10 sig det lvl = 10, note h 0.95 1.05 1.15 no signal detection threshold voltage vthns11 sig det lvl = 11, note h 1.20 1.30 1.40 v l ? m vdcthlm 0.8 1.0 1.2 dc detection threshold (dc) m ? h vdcthmh pins 39, 40, 44, 46, 48, 50, 60, 64, 66, 68, 70, 80 2.8 3.0 3.2 v dc detection threshold (s) vdcths pins 45, 47, 53, 59, 65, 67, 73, 79 0.8 1.0 1.2 v note e: this is the amplitude of the oscillation wave at the point between the crystal and the series capacitor. note f: remove the external capacitor connected with the sync filter pin (pin 14), hv sep1 = 00, sig det impe = 11. the delay time from sync1-in input (525/60i) to the sync filter waveform. note g: remove the external capacitor connected with the sync filter pin (pin 14). connect 10 k ? resistor between the sync filter pin and gnd. no input into sync1-in. measure the current (ir) on the resistor. imnsfil2xx = 3.3 / ir ? 10 k ? . note h: remove the external capacitor connected with the sync filter pin (pin 14). input a 0 v - vthnsxx [v] pulse of 15.7 khz into the sync filter pin. the pulse voltage during sig det status changes.
TB1311AFG 2006-05-29 41 test circuit v/s gnd sy1 in ar3 in y3/g3 in fb1 in/dc3(sw line1) ar2 in y1/g1 in cb1/b1 in al4 in dc7(s1) al5 in cvbs6 in cr1/r1 in hd out vd out sync filter cb1/b1 out au vcc (9v) monitor out cvbs1 out y1/g1 out ar1 out cr2/r2 out cr1/r1 out al2 out al3 out y2/g2 out cb2/b2 out ar5 in sc1 in ar4 in al3 in ar9 in/dc4(line3-1) al2 in fb2 out ar2 out cvbs2 out sync2 in v/s vcc (5v) fb1 out al1 out ar3 out cvbs5 in al9 in/dc5(line2-1) fb3 in/dc6(line1-1) cr3/r3 in cb3/b3 in fb2 in/ dc8(sw line2) 510 10 y1/g1 out cvbs1 out 10 510 10 cb1/b1 out cr1/r1 out + 47f 0.01f hd out vd out al1 out ar1 out monitor out al3 out ar3 out fb1 out 510 10 y2/g2 out 510 10 510 10 cb2/b2 out cr2/r2 out fb2 out cvbs2 out ar2 out al2 out + cvbs5 in ar2 in al2 in fb1/dc3 cr1/r1 in cb1/b1 in al9 in y1/g1 in fb3/dc6 cr3/r3 in ar3 in cb3/b3 in al3 in y3/g3 in ar4 in al4 in sy1 in cvbs6 in ar5 in al5 in fb2 /dc8 510 + + 180pf 1f 5.6k 1f 100pf 5.6k 100pf 5.6k 1f 100pf 1f 1f 5.6k 1f 100pf 5.6k 1f 100pf 5.6k 1f 100pf 1f 1f 1f 1f 100pf 5.6k 1f 100pf 5.6k 1f 100pf 1f 75 75 75 ar9 in 5.6k 1f 100pf 1f 100pf 5.6k dc5 ab ab 75 ab ab 75 75 75 75 75 sc1 in #6 #8 #10 #11 #14 #15 #17 #19 #21 #23 sw46 1f sw48 0.1f 75 0.01f 100f 0.01f 47f 0.01f 47f dc4 dc7 components in test circuits are used only to obtain and confirm the device characteristics. these components and circuits are not guaranteed to prevent malfunction or failure in the application equipment.
TB1311AFG 2006-05-29 42 application circuit 1 (typical values) TB1311AFG ar8 in/ dc1(s3) y2/g2 in v/s gnd sy1 in ar3 in y3/g3 in fb1 in/dc3(sw line1) ar2 in al1 in y1/g1 in ar1 in cb1/b1 in al4 in fb4 in/ dc11(line1-2) cr4/r4 in cr2/r2 in ar10 in/ dc9(line3-2) cb2/b2 in dc7(s1) al5 in cvbs6 in yvi out cr1/r1 in cvbs4 in hd out vd out sync filter cb1/b1 out au vcc (9v) sda scl monitor out cvbs1 out y1/g1 out ar1 out cr2/r2 out cr1/r1 out dc12(s2) sc2 in al2 out al7 in sy2 in al6 in al3 out y2/g2 out cb2/b2 out y4/g4 in vd in xtal hd in vss ar5 in sc1 in ar4 in al3 in ar9 in/dc4(line3-1) al2 in cvbs3 in sync1 in au gnd vdd (3.3v) fb2 out ar2 out cvbs2 out sync2 in v/s vcc (5v) fb1 out al1 out ar3 out ar7 in cb4/b4 in ar6 in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 cvbs5 in al8 in/ dc2(s4) al9 in/dc5(line2-1) fb3 in/dc6(line1-1) cr3/r3 in cb3/b3 in fb2 in/ dc8(sw line2) al10 in/ dc10(line2-2) 510 10 y1/g1 out cvbs1 out 10 510 10 cb1/b1 out cr1/r1 out + 47f 0.01f hd out vd out al1 out ar1 out monitor out al3 out ar3 out fb1 out 510 10 y2/g2 out 510 10 510 10 cb2/b2 out cr2/r2 out fb2 out cvbs2 out ar2 out al2 out + + sda scl 3.579545mhz 10pf 470 470 vd in 100 4.7f hd in 100 1f ar8 in al8 in cvbs4 in al1 in ar1 in cvbs3 in cvbs5 in ar2 in al2 in fb1 in r1 in ar9 in b1 in al9 in g1 in fb3 in cr3 in ar3 in cb3 in al3 in y3 in ar4 in sy1 in al4 in sc1 in cvbs6 in ar5 in al5 in fb2 in r2 in ar10 in b2 in al10 in g2 in fb4 in cr4 in ar6 in cb4 in al6 in y4 in ar7 in sy2 in al7 in sc2 in 510 i2cbus hd/vd(pc) audio 1 cvbs 3 cvbs 4 audio 8 44 dc3(sw line1) dc4(line3-1) 46 dc5(line2-1) 48 dc6(line1-1) 50 49 47 45 cr1 in cb1 in y1 in < d-pin 1 > audio 2 scart 1 audio 9 audio 5 scart 2 audio 10 audio 3 component video 3 audio 4 s-pin 1 component video 4 audio 6 audio 7 s-pin 2 1/2w 180 + 0.01f 100f + 47f 0.01f power supply vcc 5v vcc 9v + + monitor out main out sub out 39 40 dc1(s3) dc2(s4) for s-pin 3 for s-pin 4 180pf 0.1f 0.1f 5.6k 1f 100pf 1f 5.6k 1f 100pf 5.6k 1f 100pf 5.6k 1f 100pf 1f 1f 10k 10k 0.1f 0.1f 5.6k 1f 100pf 5.6k 1f 100pf 5.6k 1f 100pf 5.6k 1f 100pf 5.6k 1f 100pf 1f 1f 1f 5.6k 1f 100pf 5.6k 1f 100pf 5.6k 1f 100pf 1f 1f 1f 1f 100pf 5.6k 1f 100pf 5.6k 1f 100pf 10k 0.1f 1f 1f 1f 1f 1f 1f 1f 5.6k 1f 100pf 5.6k 1f 100pf 5.6k 1f 100pf 5.6k 1f 100pf 5.6k 1f 100pf 5.6k 1f 100pf 1f 100pf 10k 0.1f 0.1f 0.1f 0.1f 0.1f 1f 1f 1f changed by cbcr pin1 changed by cbcr pin3 changed by cbcr pin2 changed by cbcr pin4 changed by au8 pin the function of pins 46 and 48 are changed by au9 pin the function of pins 66 and 68 are changed by au10 pin 1k 1k 1k 1k dc8(sw line2) 64 dc9(line3-2) dc10(line2-2) dc11(line1-2) 70 68 66 69 67 65 cr2 in cb2 in y2 in < d-pin 2 > 0.1f 0.1f 0.1f 0.1f 1f 1f 1f 1k 1k 1k 1k 150k 5v 150k 5v amp or att 100k 100k 100k 100k 0 0 0 0 input video signals driven with low impedance. the application circuits shown in this document are examples provided for reference purposes only. thorough evaluation is required in the mass production design phase. by furnishing these examples of application circuits, toshiba does not grant the use of any industrial property rights.
TB1311AFG 2006-05-29 43 application circuit 2 (examples of connectors) 49 48 47 46 45 44 43 42 41 scart 1 2 3 5 7 9 11 13 15 17 19 21 4 6 8 10 12 14 16 18 20 ar-out al-out v-out 50 scart connector 49 48 47 46 45 44 d 50 1 2 3 5 7 9 11 13 4 6 8 10 12 14 5v d-sub15 z2.0v 1 2 3 5 7 9 11 13 4 6 8 10 12 14 15 fb1 in/dc3(sw line1) y1/g1 in cb1/b1 in cr1/r1 in ar9 in/dc4(line3-1) 49 48 47 46 45 44 al9 in/dc5(line2-1) 1f 1f 75 75 1f 50 fb3 in/dc6(line1-1) 0.1f vd in 31 30 100 4.7f hd in z2.0v 100 1f d-pin d-sub15 the application circuits shown in this document are examples provided for reference purposes only. thorough evaluation is required in the mass production design phase. by furnishing these examples of application circuits, toshiba does not grant the use of any industrial property rights.
TB1311AFG 2006-05-29 44 application circuit 3 (system configuration) (1) for nonstandard signals such as cvbs , yc (s-video), 525i, 625i or so. video sw sync block freq counting block video block pal/ntsc/secam color decoder sync processor adc pll i/p converter scaler color decoder / ip converter / ... sync-in video-in hd/vd-in sync sw the TB1311AFG does not support weak signals, ghost signals or other nonstandard signals. therefore, these signals should be dealt with through the use of another device capable of handling these signals, such as a color-decoder. in these cases, the signal switcher and the video circuits of the TB1311AFG can be used. in some cases, ?no-input detection? can be also used for these signals. the TB1311AFG cannot distinguish between component and rgb video. the different kinds of input signal should be separated through the use of different signal-specific input pins; for example, specific-purpose pins for rgb video input only or component video input only. (2) for standard component video (smpte standard) and standard rgb video (vesa standard) video sw sync block freq counting block video block pal/ntsc/secam color decoder sync processor adc pll i/p converter scaler color decoder / ip converter / ... sync-in video-in hd/vd-in sync sw the TB1311AFG can detect a format type for standard signal inputs. the application circuits shown in this document are examples provided for reference purposes only. thorough evaluation is required in the mass production design phase. by furnishing these examples of application circuits, toshiba does not grant the use of any industrial property rights. tb1311 tb1311
TB1311AFG 2006-05-29 45 package dimensions p-qfp80-1420-0.80c unit: mm weight: 1.6 g (typ.)
TB1311AFG 2006-05-29 46 about solderability, following conditions were confirmed ? solderability (1) use of sn-37pb solder bath solder bath temperature = 230c dipping time = 5 seconds the number of times = once use of r-type flux (2) use of sn-3.0ag-0.5cu solder bath solder bath temperature = 245c dipping time = 5 seconds the number of times = once use of r-type flux restrictions on product use 060116eb a ? the information contained herein is subject to change without notice. 021023_d ? toshiba is continually working to improve the quality an d reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inhe rent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc. 021023_a ? the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. 021023_b ? the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_q ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. 021023_c ? the products described in this document are subject to the foreign exchange and foreign trade laws. 021023_e

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